Question
A direct-mapped cache of 16 KB with a block size of 32 bytes is used in a system with 32-bit addresses. How many tag bits are required per cache line?
More Computer Architecture and Design Questions
- A CPU operates at a clock speed of 4 GHz, and each instruction takes an average of 2.5 clock cycles to execute (CPI = 2.5). What is the effective instructi...
- Which operating system component manages and allocates system resources among various running processes?
- A CPU operates at a clock speed of 2 GHz, and on average, each instruction takes 4 clock cycles to execute (CPI = 4). What is the effective instruction exe...
- A computer system has a cache hit ratio of 90%, a cache access time of 10 ns, and a main memory access time of 100 ns (charged only on a cache miss). What ...
- A CPU operates at a clock speed of 3.5 GHz, and each instruction takes an average of 2 clock cycles to execute (CPI = 2). What is the effective instruction...
- A 5-stage instruction pipeline has a stage delay of 2 ns. Assuming no stalls or hazards, how long does it take to execute 100 instructions?
- Which level of the memory hierarchy is located closest to the CPU and offers the smallest storage capacity but the fastest access time?
- VPN stands for:
- A processor has a 32-bit address bus and byte-addressable memory. Ignoring reserved regions, what maximum physical memory space is directly addressable?
- A direct-mapped cache of 16 KB with a block size of 32 bytes is used in a system with 32-bit addresses. How many bits are in the tag field?
Hey! Ask a query
Please enter email id
The email must be a valid email address.
Please enter Mobile Number
Please enter valid Mobile Number
Please enter your Doubt
Think You're Ready for RBI Grade B?
RBI Grade B 2026 Phase 1 Memory Based Paper
- 200 Questions with Detailed Solutions
- Section-wise Coverage (GA, English, Quant & Reasoning)