What is 'pipelining' in CPU architecture?

Pipelining is a CPU design technique where the execution of an instruction is broken into multiple stages (e.g., Fetch, Decode, Execute, Memory Access, Write-back), and while one instruction is in its Execute stage, the next instruction can simultaneously be in its Decode stage, and the one after that in its Fetch stage — overlapping the stages of different instructions rather than processing each instruction fully before starting the next. This significantly improves instruction throughput, though it introduces complications like pipeline hazards that must be carefully managed.