A processor uses a write-back cache policy rather than write-through. What is the primary trade-off this design choice introduces?

In a write-back cache, a write operation updates only the cache line initially, without immediately propagating the change to main memory; this significantly reduces memory bus traffic compared to write-through, since repeated writes to the same location don't each trigger a separate memory write. To track which cache lines contain data that hasn't yet been written back to memory, each line is marked with a 'dirty bit' — when a dirty line is eventually evicted from the cache, its updated contents are written back to memory at that point. This is the opposite of write-through (option A, which writes to both cache and memory on every operation, guaranteeing consistency at the cost of more memory traffic), and options B, C, and E describe behaviors that don't correspond to either standard write policy.