Question
In pipelining, the CPU executes each instruction in a
series of following stages: Instruction Fetching (IF) ββ> Instruction Decoding (ID) ββ> Instruction Execution (EX) ββ>__ and Register Write back (WB).Solution
The correct answer is D
Statements: E > O, S < Z, O β€ S
Conclusions:
I. E < S
II. O < Z
Statement: W>Y<X<Z=U>S; W<T ≥V
I. Y<T
II. X > V
Statements: L ≥ O = J ≥ I ≤ V; C = T ≤ J
Conclusion: I. C < L II. C = L
Statements: P < Q β€ R β€ S; P > T = V β₯ X; S β€ W = Y < U
Conclusions:
I. U > R
II. W > X
III. Q < Y
Statements: W β€ B = F; H > T; H < U < F; W β€ X < S
Conclusions:
I. W < U
II. T < B
III. X > H
Statements: A < B β€ C, A > E, F β€ B < D
Conclusions:
I. D > A
II. E < B
III. C > E
IV. D > C
Statements: W < R = T < Y = S = U β₯ V β₯ H = X
Conclusions:
I. S β₯ X
II. U > T
III. W < Y
Statements: B β₯ U > P = E β₯ X; X > K > N β₯ J
Conclusions: I. N < PΒ Β Β II. J β€ X
Statements:Q = S > T > Z; T > Y = H < I
Conclusions: I. Z > H II. I > Z
Statements: X @ Y $ Z & U, Z @ V
Conclusions: I. V # X II. V $ X
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