Question

What is the main disadvantage of using asynchronous (level-triggered) flip-flops in high-speed digital circuits?

A They consume more power compared to synchronous flip-flops. Correct Answer Incorrect Answer
B They are more prone to glitches and metastability issues. Correct Answer Incorrect Answer
C They cannot be used in clocked sequential circuits. Correct Answer Incorrect Answer
D They require more complex clock generation circuits. Correct Answer Incorrect Answer
E Both a and b Correct Answer Incorrect Answer

Solution

They are more prone to glitches and metastability issues.

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